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fujitsu microelectronics data sheet copyright?2002-2009 fujitsu microelec tronics limited all rights reserved 2009.8 for the information for microcontrolle r supports, see the following web site. this web site includes the "customer design review supplement" which provides the latest cautions on system development and the minimal requirements to be checked to prevent problems before the system development. http://edevice.fujitsu.com/micom/en-support/ 16-bit microcontroller cmos f 2 mc-16lx mb90455 series mb90f455 (s) /f456 (s) /f457 (s) mb90455 (s) /456 (s) /457 (s) /v495g description mb90455 series devices are general-purpose high-perfor mance 16-bit micro controllers designed for process control of consumer products, which r equire high-speed real-time processing. the system, inheriting the architecture of f 2 mc* family, employs additional instruction ready for high-level lan- guages, expanded addressing mode, enhanc ed multiply-divide instructions, and enriched bit-processing instruc- tions. furthermore, employment of 32-bit accumula tor achieves processing of long-word data (32 bits). the peripheral resources of mb90455 series include the following: 8/10-bit a/d converter, uart 1, 8/16-bit ppg timer, 16-bi t input-output timer (16-bit free-run timer, input capture 0, 1, 2, 3 (icu)). *: f 2 mc is the abbreviation of fujitsu flexible microcontroller. features ? clock ? built-in pll clock frequency multiplication circuit ? selection of machine clocks (pll clocks) is allowed among frequency division by two on oscillation clock, and multiplication of 1 to 4 times of oscillation clock (for 4-mhz oscillation clock, 4 mhz to 16 mhz). ? operation by sub-clock (8.192 khz) is allowed. ? minimum execution time of instructi on: 62.5 ns (when operating with 4-mh z oscillation clock, and 4-time multi- plied pll clock). (continued) ds07-13728-5e
mb90455 series 2 ds07-13728-5e ? 16 mbyte cpu memory space ? 24-bit internal addressing ? instruction system best suited to controller ? wide choice of data types (bit, byte, word, and long word) ? wide choice of addressing modes (23 types) ? enhanced multiply-divide instru ctions and reti instructions ? enhanced high-precision computing with 32-bit accumulator ? instruction system compatible with high- level language (c language) and multitask ? employing system stack pointer ? enhanced various pointer indirect instructions ? barrel shift instructions ? increased processing speed ? 4-byte instruction queue ? powerful interrupt function with 8 levels and 34 factors ? automatic data transfer fu nction independent of cpu ? expanded intelligent i/o service function (ei 2 os): maximum of 16 channels ? low power consumption (standby) mode ? sleep mode (a mode that halts cpu operating clock) ? time-base timer mode (a mode that operates oscillation clock, sub clock, time-base timer and watch timer only) ? watch mode (a mode that operate s sub clock and watch timer only) ? stop mode (a mode that stops oscillation clock and sub clock) ? cpu blocking operation mode ? process ?cmos technology ? i/o port ? general-purpose input/output port (cmos output): 34 ports(mb90f455/f456/f457, mb90455/456/457) (in- cluding 4 high-current output ports) (when sub clock is not used, 36 ports(mb90f455s/f456s/f457s, mb90455s/456s/457s)) ? timer ? time-base timer, watch timer, watchdog timer: 1 channel ? 8/16-bit ppg timer: 8-bit x 4 channels, or 16-bit x 2 channels ? 16-bit reload timer: 2 channels ? 16-bit input/output timer - 16-bit free run timer: 1 channel - 16-bit input captur e: (icu): 4 channels interrupt request is issued upon latchi ng a count value of 16-bit free run ti mer by detection of an edge on pin input. ? uart 1: 1 channel ? equipped with full-duplex double buffer ? clock-asynchronous or clock-synchronous serial transmission is available (continued)
mb90455 series ds07-13728-5e 3 (continued) ? dtp/external interrupt: 4 channels ? module for activation of expanded intelligent i/o service (ei 2 os), and generation of external interrupt. ? delay interrupt generator module ? generates interrupt request for task switching. ? 8/10-bit a/d converter: 8 channels ? resolution is selectable between 8-bit and 10-bit. ? activation by external trigger input is allowed. ? conversion time: 6.125 s (at 16-mhz machine clock, including sampling time) ? program patch function ? address matching detection for 2 address pointers.
mb90455 series 4 ds07-13728-5e product lineup (continued) part number mb90f455 (s) / f456 (s) /f457 (s) mb90455 (s) / 456 (s) /457 (s) mb90v495g parameter classification flash rom mask rom evaluation product rom capacity mb90f455 (s) : 24 kbytes mb90f456 (s) : 32 kbytes mb90f457 (s) : 64 kbytes mb90455 (s) : 24 kbytes mb90456 (s) : 32 kbytes mb90457 (s) : 64 kbytes ? ram capacity 2 kbytes 6 kbytes clock mb90f455/f456/f457 : 2 systems mb90f455s/f456s/f457s : 1 system mb90455/456/457 : 2 systems mb90455s/456s/457s : 1 system 2 systems process cmos package lqfp-48 (pin pitch 0.50 mm) pga256 operating power supply voltage 3.5 v to 5.5 v 4.5 v to 5.5 v special power supply for emulator* 1 ? none cpu functions number of basic instructions instruction bit length instruction length data bit length : 351 instructions : 8 bits and 16 bits : 1 byte to 7 bytes : 1 bit, 8 bits, 16 bits minimum instruction execution time : 62.5 ns (at 16-mhz machine clock) interrupt processing time : 1.5 s at minimum (at 16-mhz machine clock) low power consumption (standby) mode sleep mode/watch mode/time-base timer mode/ stop mode/cpu intermittent i/o port general-purpose input/output ports (cmos output) : 34 ports (36 ports* 2 ) including 4 high-current output ports (p14 to p17) time-base timer 18-bit free-run counter interrupt cycle : 1.024 ms, 4. 096 ms, 16.834 ms, 131.072 ms (with oscillation clock frequency at 4 mhz) watchdog timer reset generation cycle: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (with oscillation clock frequency at 4 mhz) 16-bit input/ output timer 16-bit free-run timer number of channels: 1 interrupt upon occurrence of overflow input capture number of channels: 4 retaining free-run timer value set by pin input (rising edge, falling edge, and both edges) 16-bit reload timer number of channels: 2 16-bit reload timer operation count clock cycle: 0.25 s, 0.5 s, 2.0 s (at 16-mhz machine clock frequency) external event count is allowed. watch timer 15-bit free-run counter interrupt cycle: 31.25 ms, 62.5 ms, 12 ms, 250 ms, 500 ms, 1.0 s, 2.0 s (with 8.192 khz sub clock)
mb90455 series ds07-13728-5e 5 (continued) *1 : settings of dip switch s2 for using emulation pod mb2145-507. for details, se e mb2145-507 hardware manual (2.7 power pin solely for emulator). *2 : mb90f455s/f456s/f457s, mb90455s/456s/457s part number mb90f455 (s) / f456 (s) /f457 (s) mb90455 (s) / 456 (s) /457 (s) mb90v495g parameter 8/16-bit ppg timer number of channels: 2 (four 8- bit channels are available also) ppg operation is allowed with four 8-bit channels or two 16-bit channels. outputting pulse wave of arbitrary cycle or arbitrary duty is allowed. count clock: 62.5 ns to 1 s (with 16 mhz machine clock) delay interrupt generator module interrupt generator module for task switching. used for real-time os. dtp/external interrupt number of inputs: 4 activated by rising edge, falling edge, ?h? level or ?l? level input. external interrupt or expan ded intelligent i/o service (ei 2 os) is available. 8/10-bit a/d converter number of channels: 8 resolution: selectable 10-bit or 8-bit. conversion time: 6.125 s (at 16-mhz machine clock, including sampling time) sequential conversion of two or more su ccessive channels is allowed. (setting a maximum of 8 channels is allowed.) single conversion mode : selected channel is converted only once. sequential conversion mode: selected channel is converted repetitively. halt conversion mode : conversion of selected channel is stopped and activated alternately. uart 1 number of channels: 1 clock-synchronous transfer: 62.5 kbps to 2 mbps clock-asynchronous transfe r: 9,615 bps to 500 kbps communication is allowed by bi-directional serial communication function and master/slave type connection.
mb90455 series 6 ds07-13728-5e packages and product models : yes : no note : refer to ? package dimension? for details of the package. product comparison memory space when testing with test product for evaluation, check the differences between the product and a product to be used actually. pay attention to the following points: ? the mb90v495g has no built-in rom. however, a sp ecial-purpose development tool allows the operations as those of one with built-in rom. rom capa city depends on settings on a development tool. ? on mb90v495g, an image from ff4000 h to ffffff h is viewed on 00 bank and an image of fe0000 h to ff3fff h is viewed only on fe bank and ff bank. (modified on se ttings of a development tool.) ? on mb90f455 (s) /f456 (s) /f457 (s) , mb90455 (s) /456 (s) /457 (s) , an image from ff4000 h to ffffff h is viewed on 00 bank and an image of fe0000 h to ff3fff h is viewed only on ff bank. package mb90f455 (s) /f456 (s) /f457 (s) mb90455 (s) /456 (s) /457 (s) fpt-48p-m26
mb90455 series ds07-13728-5e 7 pin asignment 1 2 3 4 5 6 7 8 9 10 11 12 av cc avr p50/an0 p51/an1 p52/an2 p53/an3 p54/an4 p55/an5 p56/an6 p57/an7 p37/adtg p20/tin0 36 35 34 33 32 31 30 29 28 27 26 25 p17/ppg3 p16/ppg2 p15/ppg1 p14/ppg0 p13/in3 p12/in2 p11/in1 p10/in0 x1 x0 c v ss 48 47 46 45 44 43 42 41 40 39 38 37 av ss x1a/p36* x0a/p35* p33 p32 p31 p30 p44 p43 p42/sot1 p41/sck1 p40/sin1 13 14 15 16 17 18 19 20 21 22 23 24 p21/tot0 p22/tin1 p23/tot1 p24/int4 p25/int5 p26/int6 p27/int7 md2 md1 md0 rst v cc (fpt-48p-m26) (top view) * : mb90f455/f456/f457, mb90455/456/457 : x1a, x0a mb90f455s/f456s/f457s, mb90455s/456s/457s : p36, p35
mb90455 series 8 ds07-13728-5e pin description (continued) pin no. pin name circuit format description 1avcc ? vcc power input pin for a/d converter 2 avr ? power (vref+) input pin for a/d converter. use as input for vcc or lower. 3 to 10 p50 to p57 e general-purpose input/output ports. an0 to an7 functions as an analog input pin for a/d converter. valid when analog input setting is ?enabled.? 11 p37 d general-purpose input/output port. adtg function as an external trigger input pin for a/d converter. use the pin by setting as input port. 12 p20 d general-purpose input/output port. tin0 function as an event input pin for reload timer 0. use the pin by setting as input port. 13 p21 d general-purpose input/output port. tot0 function as an event output pin for reload timer 0. valid only when output setting is ?enabled.? 14 p22 d general-purpose input/output port. tin1 function as an event input pin for reload timer 1. use the pin by setting as input port. 15 p23 d general-purpose input/output port. tot1 function as an event output pin for reload timer 1. valid only when output setting is ?enabled.? 16 to 19 p24 to p27 d general-purpose input/output ports. int4 to int7 functions as an external interrupt input pin. use the pin by setting as input port. 20 md2 f input pin for specifying operatio n mode. connect directly to vss. 21 md1 c input pin for specifying operatio n mode. connect directly to vcc. 22 md0 c input pin for specifying operatio n mode. connect directly to vcc. 23 rst b external reset input pin. 24 vcc ? power source (5 v) input pin. 25 vss ? power source (0 v) input pin. 26 c ? capacitor pin for stabilizing power sour ce. connect a ceramic capacitor of approximately 0.1 f. 27 x0 a pin for high-rate oscillation. 28 x1 a pin for high-rate oscillation. 29 to 32 p10 to p13 d general-purpose input/output ports. in0 to in3 functions as trigger input pins of i nput capture channels 0 to 3. use the pins by setting as input ports.
mb90455 series ds07-13728-5e 9 (continued) * : mb90f455/f456/f457, mb90455/456/457 : x1a, x0a mb90f455s/f456s/f457s, mb90455s/456s/457s : p36, p35 pin no. pin name circuit format description 33 to 36 p14 to p17 g general-purpose input/output ports. high-current output ports. ppg0 to ppg3 functions as output pins of ppg timers 01 and 23. valid when output setting is ?enabled.? 37 p40 d general-purpose input/output port. sin1 serial data input pin for uart. us e the pin by setting as input port. 38 p41 d general-purpose input/output port. sck1 serial clock input pin for uart. valid only when serial clock input/output setting on uart is ?enabled.? 39 p42 d general-purpose input/output port. sot1 serial data input pin for uart. valid only when serial data input/output setting on uart is ?enabled.? 40 p43 d general-purpose input/output port. 41 p44 d general-purpose input/output port. 42 to 45 p30 to p33 d general-purpose input/output ports. 46 x0a* a pin for low-rate oscillation. p35* general-purpose input/output port. 47 x1a* a pin for low-rate oscillation. p36* general-purpose input/output port. 48 avss ? vss power source input pin for a/d converter.
mb90455 series 10 ds07-13728-5e i/o circuit type (continued) type circuit remarks a ? high-rate oscillation feedback resistor, approx.1 m ? low-rate oscillation feedback resistor, approx.10 m b ? hysteresis input with pull-up resistor. ? pull-up resistor, approx.50 k c ? hysteresis input d ? cmos hysteresis input ? cmos level output ? standby control provided e ? cmos hysteresis input ? cmos level output ? shared for analog input pin ? standby control provided x1 x1a x0 x0a clock input standby control signal r vcc r hysteresis input r hysteresis input r pch nch vcc vss digital output digital output hysteresis input standby control r pch nch vcc vss digital output digital output hysteresis input standby control analog input
mb90455 series ds07-13728-5e 11 (continued) type circuit remarks f ? hysteresis input with pull-down resistor ? pull-down resistor, approx. 50 k ? flash product is not provided with pull-down resistor. g ? cmos hysteresis input ? cmos level output (high-current output) ? standby control provided vss r r hysteresis input r pch nch vcc vss high-current output high-current output hysteresis input standby control
mb90455 series 12 ds07-13728-5e handling devices ? do not exceed maximum rati ng (preventing ?latch up?) ? on a cmos ic, latch-up may occur when applying a volt age higher than vcc or a voltage lower than vss to input or output pin, which has no middle or high wi thstand voltage. latch-up may also occur when a voltage exceeding maximum rating is applied across vcc and vss. ? latch-up causes drastic increase of power current, whic h may lead to destruction of elements by heat. extreme caution must be taken not to exceed maximum rating. ? when turning on and off analog power source, take extr a care not to apply an analog power voltages (avcc and avr) and analog input voltage that ar e higher than digital power voltage (vcc). ? handling unused pins ? leaving unused input pins open ma y cause permanent destruction by malfunction or latch-up. apply pull-up or pull-down process to the unused pins using resistors of 2 k or higher. leave unused input/output pins open under output status, or process as inpu t pins if they are under input status. ? using external clock ? when using an external clock, drive only x0 pin and leave x1 pin open. an example of using an external clock is shown below. using external clock ? notes when using no sub clock ? if an oscillator is not connected to x0a and x1a pin, appl y pull-down resistor to x0a pin and leave x1a pin open. ? about power supply pins ? if two ore more vcc and vss exist, the pins that should be at the same potential are connected to each other inside the device. for reducing unwanted emissions and preventing malfunction of strobe signals caused by increase of ground level, however, be sure to connect the vcc and vss pi ns to the power source and the ground externally. ? pay attention to connect a power supply to vcc and vss of mb90455 series device in a lowest-possible impedance. ? near pins of mb90455 series device, connecti ng a bypass capacitor is recommended at 0.1 f across vcc and vss. ? crystal oscillator circuit ? noises around x0 and x1 pins cause malfunctions on a mb90455 series device. design a print circuit so that x0 and x1 pins, an crystal oscillator (or a ceramic osc illator), and bypass capacitor to the ground become as close as possible to each other. furthermore, avoid wire s to x0 and x1 pins crossing each other as much as possible. ? print circuit designing that surrounds x0 and x1 pins with grounding wires, which ensures stable operation, is strongly recommended. x1 x0 open mb90455 series
mb90455 series ds07-13728-5e 13 ? caution on operations during pll clock mode ? if the pll clock mode is selected, the microcontroller at tempt to be working with the self-oscillating circuit even when there is no external oscillator or external cloc k input is stopped. performance of this operation, however, cannot be guaranteed. ? sequence of turning on power of a/ d converter and applying analog input ? be sure to turn on digital power (vcc) before apply ing signals to the a/d converter and applying analog input signals (an0 to an7 pins). ? be sure to turn off the power of a/ d converter and analog input before turning off the digital power source. ? be sure not to apply avr exceeding avcc when turning on and off. (no pr oblems occur if analog and digital power is turned on and off simultaneously.) ? handling pins when a/d converter is not used ? if the a/d converter is not used, connect the pins under the following conditions: ?avcc=avr=vcc,? and ?avss=vss? ? note on turning on power ? for preventing malfunctions on built-in st ep-down circuit, maintain a minimum of 50 s of voltage rising time (between 0.2 v and 2.7 v) when turning on the power. ? stabilization of supply voltage ? a sudden change in the supply voltage may cause the device to malfunction even within the specified vcc supply voltage operating range. therefore, the vcc supply voltage should be stabilized. for reference, the supply voltage should be controlled so that vcc ripple variations (peak-to-peak values) at commercial frequencies (50 hz to 60 hz) fall below 10 % of the standard v cc supply voltage and the coefficient of fluctuation does not exceed 0.1 v/ms at instantaneous power switching.
mb90455 series 14 ds07-13728-5e block diagram in0 ~ in3 ram rom/flash int4 ~ int7 ppg0 ~ ppg3 tin0,tin1 tot0,tot1 x0a,x1a rst x0,x1 sck1 sot1 sin1 avcc an0 ~ an7 avss avr adtg uart1 clock control circuit watch timer time-base timer prescaler cpu f 2 mc-16lx core 16-bit free-run timer input capture (4ch) 16-bit ppg timer (2ch) 16-bit reload timer (2ch) dtp/external interrupt 8/10-bit a/d converter (8ch) internal data bus
mb90455 series ds07-13728-5e 15 memory map mb90455 series allows specifying a memo ry access mode ?single chip mode?. 1. memory allocation of mb90455 mb90455 series model has 24-bit wide internal address bus and up to 24-bit bus of external address bus. a maximum of 16 mbyte memory space of external access memory is accessible. 2. memory map note : when internal rom is operating, f 2 mc-16lx allows viewing rom data im age on ff bank at upper-level of 00 bank. this function is called ?mirroring rom,? wh ich allows effective use of c compiler small model. f 2 mc-16lx assigns the same low order 16-bit address to ff bank and 00 bank, which allows referencing table in rom without specifying ?far? using pointer. for example, when accessing to ?00c000 h ?, rom data at ?ffc000 h ? is accessed actually. however, because rom area of ff bank exceeds 48 kbytes, viewing all areas is not possible on 00 bank image. because rom data of ?ff4000 h ? to ?ffffff h ? is viewed on ?004000 h ? to ?00ffff h ? image, store a rom data table in area ?ff4000 h ? to ?ffffff h ?. ffffff h fe0000 h 010000 h 003800 h 004000 h 000100 h 0000c0 h 000000 h ff0000 h (with rom mirroring function available) peripheral ram area register extension io area rom area (ff bank image) rom area address #1* 1 : internal access memory : access disallowed *1 : addresses #1 and #3 are product-specific. *2 : on mb90f455 (s) /f456 (s) /f457 (s) , 455 (s) /456 (s) /457 (s) , to read ?fe0000 h ? to ?feffff h ? is to read out ?ff0000 h ? to ?ffffff h ?. rom area* 2 (with rom mirroring function not available) peripheral ram area register extension io area rom area rom area* 2 product address #1* 1 address #2* 1 mb90f455 (s) /455 (s) 000900 h ffa000 h mb90f456 (s) /456 (s) 000900 h ff8000 h mb90f457 (s) /457 (s) 000900 h ff0000 h mb90v495g 001900 h ? address #2* 1
mb90455 series 16 ds07-13728-5e i/o map (continued) address register abbreviation register name reset value peripheral function name read/ write 000000 h (reserved area) * 000001 h pdr1 port 1 data register xxxxxxxx b port 1 r/w 000002 h pdr2 port 2 data register xxxxxxxx b port 2 r/w 000003 h pdr3 port 3 data register xxxxxxxx b port 3 r/w 000004 h pdr4 port 4 data register xxxxxxxx b port 4 r/w 000005 h pdr5 port 5 data register xxxxxxxx b port 5 r/w 000006 h to 000010 h (reserved area) * 000011 h ddr1 port 1 direction data register 00000000 b port 1 r/w 000012 h ddr2 port 2 direction data register 00000000 b port 2 r/w 000013 h ddr3 port 3 direction data register 000x0000 b port 3 r/w 000014 h ddr4 port 4 direction data register xxx00000 b port 4 r/w 000015 h ddr5 port 5 direction data register 00000000 b port 5 r/w 000016 h to 00001a h (reserved area) * 00001b h ader analog input permission register 11111111 b 8/10-bit a/d converter r/w 00001c h to 000025 h (reserved area) * 000026 h smr1 serial mode register 1 00000000 b uart1 r/w 000027 h scr1 serial control register 1 00000100 b r/w, w 000028 h sidr1/ sodr1 serial input data register 1/ serial output data register 1 xxxxxxxx b r, w 000029 h ssr1 serial status data register 1 00001000 b r, r/w 00002a h (reserved area) * 00002b h cdcr1 communication prescaler control register 1 0xxx0000 b uart1 r/w 00002c h to 00002f h (reserved area) * 000030 h enir dtp/external interrupt permission register 00000000 b dtp/external interrupt r/w 000031 h eirr dtp/external interrupt permission register xxxxxxxx b r/w 000032 h (reserved area) * 000033 h elvr detection level setting register 00000000 b dtp/external interrupt r/w
mb90455 series ds07-13728-5e 17 (continued) address register abbreviation register name reset value peripheral function name read/ write 000034 h adcs a/d control status register 00000000 b 8/10-bit a/d converter r/w 000035 h 00000000 b r/w, w 000036 h adcr a/d data register xxxxxxxx b w, r 000037 h 00101xxx b r 000038 h to 00003f h (reserved area) * 000040 h ppgc0 ppg0 operation mode control register 0x000xx1 b 8/16-bit ppg timer 0/1 r/w, w 000041 h ppgc1 ppg1 operation mode control register 0x000001 b r/w, w 000042 h ppg01 ppg0/1 count clock selection register 000000xx b r/w 000043 h (reserved area) * 000044 h ppgc2 ppg2 operation mode control register 0x000xx1 b 8/16-bit ppg timer 2/3 r/w, w 000045 h ppgc3 ppg3 operation mode control register 0x000001 b r/w, w 000046 h ppg23 ppg2/3 count clock selection register 000000xx b r/w 000047 h to 00004f h (reserved area) * 000050 h ipcp0 input capture data register 0 xxxxxxxx b 16-bit input/output timer r 000051 h xxxxxxxx b 000052 h ipcp1 input capture data register 1 xxxxxxxx b r 000053 h xxxxxxxx b 000054 h ics01 input capture control status register 00000000 b r/w 000055 h ics23 00000000 b 000056 h tcdt timer counter data register 00000000 b r/w 000057 h 00000000 b 000058 h tccs timer counter control status register 00000000 b r/w 000059 h (reserved area) * 00005a h ipcp2 input capture data register 2 xxxxxxxx b 16-bit input/output timer r 00005b h xxxxxxxx b 00005c h ipcp3 input capture data register 3 xxxxxxxx b r 00005d h xxxxxxxx b
mb90455 series 18 ds07-13728-5e (continued) address register abbreviation register name reset value peripheral function name read/ write 00005e h to 000065 h (reserved area) * 000066 h tmcsr0 timer control status register 00000000 b 16-bit reload timer 0 r/w 000067 h xxxx0000 b r/w 000068 h tmcsr1 00000000 b 16-bit reload timer 1 r/w 000069 h xxxx0000 b r/w 00006a h to 00006e h (reserved area) * 00006f h romm rom mirroring function selection register xxxxxxx1 b rom mirroring function selection module w 000070 h to 00007f h (reserved area) * 000080 h to 00008f h (reserved area) * 000090 h to 00009d h (reserved area) * 00009e h pacsr address detection control register 00000000 b address matching detection function r/w 00009f h dirr delay interrupt request generation/ release register xxxxxxx0 b delay interrupt generation module r/w 0000a0 h lpmcr lowe power consumption mode control register 00011000 b lowe power consumption mode w,r/w 0000a1 h ckscr clock selection register 11111100 b clock r,r/w 0000a2 h to 0000a7 h (reserved area) * 0000a8 h wdtc watchdog timer control register xxxxx111 b watchdog timer r,w 0000a9 h tbtc time-base timer control register 1xx00100 b time-base timer r/w,w 0000aa h wtc watch timer control register 1x001000 b watch timer r,r/w 0000ab h to 0000ad h (reserved area) *
mb90455 series ds07-13728-5e 19 (continued) address register abbreviation register name reset value peripheral function name read/ write 0000ae h fmcs flash memory control status register 000x0000 b 512 k-bit flash memory r,w,r/w 0000af h (reserved area) * 0000b0 h icr00 interrupt control register 00 00000111 b interrupt controller r/w 0000b1 h icr01 interrupt control register 01 00000111 b 0000b2 h icr02 interrupt control register 02 00000111 b 0000b3 h icr03 interrupt control register 03 00000111 b 0000b4 h icr04 interrupt control register 04 00000111 b 0000b5 h icr05 interrupt control register 05 00000111 b 0000b6 h icr06 interrupt control register 06 00000111 b 0000b7 h icr07 interrupt control register 07 00000111 b 0000b8 h icr08 interrupt control register 08 00000111 b 0000b9 h icr09 interrupt control register 09 00000111 b 0000ba h icr10 interrupt control register 10 00000111 b 0000bb h icr11 interrupt control register 11 00000111 b 0000bc h icr12 interrupt control register 12 00000111 b 0000bd h icr13 interrupt control register 13 00000111 b 0000be h icr14 interrupt control register 14 00000111 b 0000bf h icr15 interrupt control register 15 00000111 b 0000c0 h to 0000ff h (reserved area) * 001ff0 h padr0 detection address setting register 0 (low-order) xxxxxxxx b address matching detection function r/w 001ff1 h detection address setting register 0 (middle-order) xxxxxxxx b 001ff2 h detection address setting register 0 (high-order) xxxxxxxx b 001ff3 h padr1 detection address setting register 1 (low-order) xxxxxxxx b r/w 001ff4 h detection address setting register 1 (middle-order) xxxxxxxx b 001ff5 h detection address setting register 1 (high-order) xxxxxxxx b 003900 h tmr0/ tmrlr0 16-bit timer register 0/16-bit reload register xxxxxxxx b 16-bit reload timer 0 r,w 003901 h xxxxxxxx b
mb90455 series 20 ds07-13728-5e (continued) reset values : 0 : reset value of this bit is ?0.? 1 : reset value of this bit is ?1.? x : reset value of this bit is undefined. * : ?reserved area? should not be written anything. result of reading from ?reserved area? is undefined. address register abbreviation register name reset value peripheral function name read/ write 003902 h tmr1/ tmrlr1 16-bit timer register 1/16-bit reload register xxxxxxxx b 16-bit reload timer 1 r,w 003903 h xxxxxxxx b 003904 h to 00390f h (reserved area) * 003910 h prll0 ppg0 reload register l xxxxxxxx b 8/16-bit ppg timer r/w 003911 h prlh0 ppg0 reload register h xxxxxxxx b r/w 003912 h prll1 ppg1 reload register l xxxxxxxx b r/w 003913 h prlh1 ppg1 reload register h xxxxxxxx b r/w 003914 h prll2 ppg2 reload register l xxxxxxxx b r/w 003915 h prlh2 ppg2 reload register h xxxxxxxx b r/w 003916 h prll3 ppg3 reload register l xxxxxxxx b r/w 003917 h prlh3 ppg3 reload register h xxxxxxxx b r/w 003918 h to 003bff h (reserved area) * 003c00 h to 003c0f h ram (general purpose ram) 003c10 h to 003fff h (reserved area) *
mb90455 series ds07-13728-5e 21 interrupt sources, interrupt vectors , and interrupt control registers (continued) interrupt source ei 2 os readiness interrupt vector interrupt control register priority* 3 number address icr address reset #08 08 h ffffdc h ?? high int 9 instruction #09 09 h ffffd8 h ?? exceptional treatment #10 0a h ffffd4 h ?? reserved #11 0b h ffffd0 h icr00 0000b0 h reserved #12 0c h ffffcc h reserved #13 0d h ffffc8 h icr01 0000b1 h reserved #14 0e h ffffc4 h reserved #15 0f h ffffc0 h icr02 0000b2 h time-base timer #16 10 h ffffbc h 16-bit reload timer 0 #17 11 h ffffb8 h icr03 0000b3 h * 1 8/10-bit a/d converter #18 12 h ffffb4 h 16-bit free-run timer overflow #19 13 h ffffb0 h icr04 0000b4 h reserved #20 14 h ffffac h reserved #21 15 h ffffa8 h icr05 0000b5 h ppg timer ch0, ch1 underflow #22 16 h ffffa4 h input capture 0-input #23 17 h ffffa0 h icr06 0000b6 h * 1 external interrupt (int4/int5) #24 18 h ffff9c h input capture 1-input #25 19 h ffff98 h icr07 0000b7 h * 2 ppg timer ch2, ch3 underflow #26 1a h ffff94 h external interrupt (int6/int7) #27 1b h ffff90 h icr08 0000b8 h * 1 watch timer #28 1c h ffff8c h reserved #29 1d h ffff88 h icr09 0000b9 h input capture 2-input input capture 3-input #30 1e h ffff84 h reserved #31 1f h ffff80 h icr10 0000ba h reserved #32 20 h ffff7c h reserved #33 21 h ffff78 h icr11 0000bb h reserved #34 22 h ffff74 h reserved #35 23 h ffff70 h icr12 0000bc h 16-bit reload timer 1 #36 24 h ffff6c h low
mb90455 series 22 ds07-13728-5e (continued) : available : unavailable : available el 2 os function is provided. : available when a cause of interr upt sharing a same icr is not used. *1: ? peripheral functions sharing an icr regi ster have the same interrupt level. ? if peripheral functions share an icr register, only one function is available when using expanded intelligent i/o service (ei 2 os) . ? if peripheral functions share an icr register, a function using expanded in telligent i/o service (ei 2 os) does not allow interrupt by another function. *2: input capture 1 is ready only for ei 2 os, and ppg is not ready for ei 2 os. disable ppg interrupt when using ei 2 os with input capture 1. *3: priority when two or more interrupts of a same level occur simultaneously. cause of interrupt ei 2 os readiness interrupt vector interrupt control register priority* 3 number address icr address uart1 reception completed #37 25 h ffff68 h icr13 0000bd h * 1 high uart1 transmission completed #38 26 h ffff64 h reserved #39 27 h ffff60 h icr14 0000be h reserved #40 28 h ffff5c h flash memory #41 29 h ffff58 h icr15 0000bf h delay interrupt generation module #42 2a h ffff54 h low
mb90455 series ds07-13728-5e 23 peripheral resources 1. i/o ports the i/o ports are used as general-purpose input/output ports (parallel i/o ports). the mb90455 series model is provided with 5 ports (34 inputs). the ports func tion as input/output pins for peripheral functions also. ? i/o port functions an i/o port, using port data resister (pdr), outputs the output data to i/o pin and input a signal input to i/o port. the port direction register (ddr) specifies direction of input/output of i/o pins on a bit-by-bit basis. the following summarizes functions of th e ports and sharing peripheral functions : ? port 1 : general-purpose input/output port, used also for ppg timer output and input capture inputs. ? port 2 : general-purpose input/output port, used also fo r reload timer input/output and external interrupt input. ? port 3 : general-purpose input/output port, used also for a/d converter activation trigger pin. ? port 4 : general-purpose input/output port, used also for uart input/output. ? port 5 : general-purpose input/output port, used also analog input pin. ? port 1 pins block diagram (single-chip mode) ? port 1 registers (single-chip mode) ? port 1 registers include port 1 data register (p dr1) and port 1 direction register (ddr1). ? the bits configuring the register corres pond to port 1 pins on a one-to-one basis. relation between port 1 registers and pins port name bits of register and corresponding pins port 1 pdr1, ddr1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 corresponding pins p17 p16 p15 p14 p13 p12 p11 p10 pch nch peripheral function input peripheral function output port data register (pdr) pdr read output latch pdr write peripheral function output permission pin port direction register (ddr) direction latch ddr write ddr read standby control (spl=1) standby control : control among stop mode (spl=1), time-base timer mode (spl=1), and watch mode (spl=1). internal data bus
mb90455 series 24 ds07-13728-5e ? port 2 pins block diagram (general-purpose input/output port) ? port 2 registers ? port 2 registers include port 2 data register (p dr2) and port 2 direction register (ddr2). ? the bits configuring the register corres pond to port 2 pins on a one-to-one basis. relation between port 2 registers and pins port name bits of register and corresponding pins port 2 pdr2,ddr2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 corresponding pins p27 p26 p25 p24 p23 p22 p21 p20 pch nch peripheral function input peripheral function output port data register (pdr) pdr read output latch pdr write peripheral function output permission pin port direction register (ddr) direction latch ddr write ddr read standby control (spl=1) standby control : control among stop mode (spl=1 ), time-base timer mode (spl=1), and watch mode (spl=1). internal data bus
mb90455 series ds07-13728-5e 25 ? port 3 pins block diagram (general-purpose input/output port) ? port 3 registers ? port 3 registers include port 3 data register (p dr3) and port 3 direction register (ddr3). ? the bits configuring the register corres pond to port 3 pins on a one-to-one basis. relation between port 3 registers and pins * : p35 and p36 do not exist on mb 90f455/f456/f457, and mb90455/456/457. port name bits of register and corresponding pins port 3 pdr3, ddr3 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 corresponding pins p37 p36* p35* ? p33 p32 p31 p30 pch nch peripheral function input peripheral function output port data register (pdr) pdr read output latch pdr write peripheral function output permission pin port direction register (ddr) direction latch ddr write ddr read standby control (spl=1) internal data bus standby control : control among stop mode (spl=1), time-base timer mode (spl=1), and watch mode (spl=1).
mb90455 series 26 ds07-13728-5e ? port 4 pins block diagram ? port 4 registers ? port 4 registers include port 4 data register (p dr4) and port 4 direction register (ddr4). ? the bits configuring the register corres pond to port 4 pins on a one-to-one basis. relation between port 4 registers and pins port name bits of register and corresponding pins port 4 pdr4, ddr4 ??? bit4 bit3 bit2 bit1 bit0 corresponding pins ??? p44 p43 p42 p41 p40 pch nch peripheral function input peripheral function output port data register (pdr) pdr read output latch pdr write peripheral function output permission pin port direction register (ddr) direction latch ddr write ddr read standby control (spl=1) internal data bus standby control : control among stop mode (spl=1), time-base timer mode (spl=1), and watch mode (spl=1).
mb90455 series ds07-13728-5e 27 ? port 5 pins block diagram ? port 5 registers ? port 5 registers include port 5 data register (pdr5) , port 5 direction register (ddr5), and analog input permission register (ader). ? analog input permission register (ader) allows or di sallows input of analog signal to the analog input pin. ? the bits configuring the register corres pond to port 5 pins on a one-to-one basis. relation between port 5 registers and pins port name bits of register and corresponding pins port 5 pdr5, ddr5 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ader ade7 ade6 ade5 ade4 ade3 ade2 ade1 ade0 corresponding pins p57 p56 p55 p54 p53 p52 p51 p50 ader pch nch standby control: control among stop mode (spl=1), time-base timer mode (spl=1), and watch mode (spl=1). port data register (pdr) pdr read output latch pdr write pin port direction register (ddr) direction latch ddr write ddr read standby control (spl=1) internal data bus analog input
mb90455 series 28 ds07-13728-5e 2. time-base timer the time-base time is a 18-bit free-run counter (time- base timer counter) that counts up in synchronization with the main clock (dividing main oscillation clock by 2). ? four choices of interval time are selectable, and generation of interrupt request is allowed for each interval time. ? provides operation clock signal to oscillation st abilizing wait timer and peripheral functions. ? interval timer function ? when the counter of time-base timer reaches an interv al time specified by interval time selection bit (tbtc:tbc1, tbc0), an overflow (carrying-over) occu rs (tbtc: tbof=1) and interrupt request is generated. ? if an interrupt by overflow is permitted (tbtc: tbie=1), an interrupt is generated when overflow occurs (tbtc: tbof=1). ? the following four interval time settings are selectable : interval time of time-base timer hclk: oscillation clock values in parentheses ?( )? are those u nder operation of 4-mhz oscillation clock. count clock interval time 2/hclk (0.5 s) 2 12 /hclk (approx. 1.0 ms) 2 14 /hclk (approx. 4.1 ms) 2 16 /hclk (approx. 16.4 ms) 2 19 /hclk (approx. 131.1 ms)
mb90455 series ds07-13728-5e 29 ? time-base timer block diagram actual interrupt request number of time-base timer is as follows: interrupt request number: #16 (10 h ) 2 1 /hclk cks cr : mcs = 1 0* 1 cks cr : scs = 0 1* 2 of of of of tbie tbof tbc1 tbc0 tbr 2 1 2 2 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 2 10 2 9 2 8 2 3 to ppg timer time-base timer counter to watchdog timer to clock controller oscillation stabilizing wait time selector interval timer selector counter- clear circuit power-on reset stop mode tbof clear tbof set time-base timer control register (tbtc) re- served of : overflow hclk : oscillation clock *1 : switch machine clock from main clock to pll clock. *2 : switch machine clock from sub clock to main clock. time-base timer interrupt signal
mb90455 series 30 ds07-13728-5e 3. watchdog timer the watchdog timer is a 2-bit counter that uses time-base timer or watch timer as count clock. if the counter is not cleared within an interval time, cpu is reset. ? watchdog timer functions ? the watchdog timer is a timer counter that prevents runa way of a program. once a watchdog timer is activated, the counter of watchdog timer must always be cleared wi thin a specified time of interval. if specified interval time elapses without clearing the counter of a watchdog ti mer, cpu resetting occurs. this is the function of a watchdog timer. ? the interval time of a watchdog timer is determined by a clock cycle, which is input as a count clock. watchdog resetting occurs between a minimum time and a maximum time specified. ? the output target of a clock source is specified by the watchdog clock selection bi t (wtc: wdcs) in the watch timer control register. ? interval time of a watchdog timer is specified by t he time-base timer output selection bit/watch timer output selection bit (wdtc: wt1, wt0) in the watchdog timer control register. interval timer of watchdog timer hclk: oscillation clock ( 4 mhz) , csclk: sub clock (8.192 khz) notes: ? if the time-base timer is cleared when watchdog ti mer count clock is used as time base timer output (carry-over signal), watchdog reset time may become longer. ? when using the sub clock as machine clock, be sure to specify watchdog timer clock source selection bit (wdcs) in watch timer control register (wtc ) at ?0,? selecting output of watch timer. min max clock cycle min max clock cycle approx. 3.58 ms approx. 4.61 ms 2 14 2 11 /hclk approx. 0.457 s approx. 0.576 s 2 12 2 9 /sclk approx. 14.33 ms approx. 18.3 ms 2 16 2 13 /hclk approx. 3.584 s approx. 4.608 s 2 15 2 12 /sclk approx. 57.23 ms approx. 73.73 ms 2 18 2 15 /hclk approx. 7.168 s approx. 9.216 s 2 16 2 13 /sclk approx. 458.75 ms approx. 589.82 ms 2 21 2 18 /hclk approx. 14.336 s approx. 18.432 s 2 17 2 14 /sclk
mb90455 series ds07-13728-5e 31 ? watchdog timer block diagram 2 1 2 2 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 2 10 2 9 2 8 2 srst wt1 wt0 wte ponr wrst erst wdcs 2 1 2 2 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 7 2 6 2 5 4 4 watchdog timer control register(wdtc) watch timer control register (wtc) watchdog timer reset occurs shift to sleep mode shift to time-base timer mode shift to watch mode shift to stop mode counter clear control circuit count clock selector 2-bit counter watchdog reset generation circuit internal reset generation circuit clear main clock (dividing hclk by 2) sub clock sclk time-base timer counter watch counter hclk: oscillation clock sclk: sub clock activate
mb90455 series 32 ds07-13728-5e 4. 16-bit input/output timer the 16-bit input/output timer is a comp ound module composed of 16-bit free-ru n timer, (1 unit) and input capture (2 units, 4 input pins). the timer, using the 16-bit free -run timer as a basis, enables measurement of clock cycle of an input signal and its pulse width. ? configuration of 16-bit input/output timer the 16-bit input/output timer is composed of the following modules: ? 16-bit free-run timer (1 unit) ? input capture (2 units, 2 input pins per unit) ? functions of 16-bit input/output timer (1) functions of 16-bit free-run timer the 16-bit free-run timer is composed of 16-bit up counter, timer counter control stat us register, and prescaler. the 16-bit up counter increments in synchronization with dividing ratio of machine clock. ? count clock is set among four ty pes of machine clock dividing rates. ? generation of interrupt is allo wed by counter value overflow. ? activation of expanded intelligent i/o service (ei 2 os) is allowed by interrupt generation. ? counter value of 16-bit free-run timer is cleared to ?0000 h ? by either resetting or software-clearing with timer count clear bit (tccs: clr). ? counter value of 16-bit free-run timer is output to input capture, which is available as base time for capture operation. (2) functions of input capture the input capture, upon detecting an edge of a signal input to the input pin from external device, stores a counter value of 16-bit free-run timer at the time of detection into the input capture data register. the function includes the input capture data registers corresponding to four i nput pins, input capture control status register, and edge detection circuit. ? rising edge, falling edge, and both ed ge are selectable for detection. ? generating interrupt on cpu is allowed by detecting an edge of input signal. ? expanded intelligent i/o service (ei 2 os) is activated by interrupt generation. ? the four input capture input pins and input capture data r egisters allows monitoring of a maximum of four events.
mb90455 series ds07-13728-5e 33 ? 16-bit input/output timer block diagram ? 16-bit free-run timer counter value of 16-bit free-run timer is used as reference time (base time) of input capture. ? input capture input capture detects rising edge, falling edge or both edges and retains a counter value of 16-bit free-run timer. detection of edge on input signal is allowed to generate interrupt. ? 16-bit free-run timer block diagram internal data bus input capture special- purpose bus 16-bit free-run timer ivf ivfe clk2 clk1 clk0 stop clr clk stop clr 2 of re- served 16-bit free-run timer timer counter data register (tcdt) output counter value to input capture prescaler timer counter control status register (tccs) free-run timer interrupt request : machine clock of : overflow internal data bus
mb90455 series 34 ds07-13728-5e ? detailed pin assignment on block diagram the 16-bit input/output timer includes a 16-bit free-run timer. interrupt request number of the 16-bit free-run timer is as follows: interrupt request number: 19 (13 h ) ? prescaler the prescaler divides a machine clock and provides a c ounter clock to the 16-bit up counter. dividing ratio of the machine clock is specified by timer counter c ontrol status register (tccs) among four values. ? timer counter data register (tcdt) the timer counter data register is a 16-bit up counter. a current counter valu e of the 16-bit free-run timer is read. writing a value during halt of the counter allows setting an arbitrary counter value.
mb90455 series ds07-13728-5e 35 ? input capture block diagram eg00 eg01 eg10 eg11 ice0 ice1 icp0 icp1 in1 in0 2 2 2 2 eg00 eg01 eg10 eg11 ice0 ice1 icp0 icp1 eg00 eg01 eg10 eg11 ice0 ice1 icp0 icp1 in3 in2 16-bit free-run timer input capture data register 3 (ipcp3) input capture data register 2 (ipcp2) edge detection circuit pin pin input capture control status register (ics23) input capture interrupt request input capture control status register (ics01) input capture data register 1 (ipcp1) pin pin edge detection circuit input capture data register 0 (ipcp0) internal data bus
mb90455 series 36 ds07-13728-5e 5. 16-bit reload timer the 16-bit reload timer has the following functions: ? count clock is selectable among 3 internal clocks and external event clock. ? activation trigger is selectable between software trigger and external trigger. ? generation of cpu interrupt is allowed upon occurrence of underflow on 16-bit timer register. available as an interval timer using the interrupt function. ? when underflow of 16-bit timer register (tmr) occurs , one of two reload modes is selectable between one- shot mode that halts counting operat ion of tmr, and reload mode that relo ads 16-bit reload register value to tmr, continuing tmr counting operation. ? the 16-bit reload timer is ready for expanded intelligent i/o service (ei 2 os). ? mb90455 series device has 2 channels of built-in 16-bit reload timer. ? operation mode of 16-bit reload timer ? internal clock mode ? the 16-bit reload timer is set to internal clock mode , by setting count clock selection bit (tmcsr: csl1, csl0) to ?00 b ?, ?01 b ?, ?10 b ?. ? in the internal clock mode, the counter decrem ents in synchronization with the internal clock. ? three types of count clock cycles are selectable by count clock selection bit (tmcsr: csl1, csl0) in timer control status register. ? edge detection of software trigger or external trigger is specified as an activation trigger. count clock activation trigger operation upon underflow internal clock mode software trigger, external trigger one-shot mode, reload mode event count mode software trigger one-shot mode, reload mode
mb90455 series ds07-13728-5e 37 ? 16-bit reload timer block diagram csl1 csl0 mod2 mod1 outl oute reld inte uf cnte trg mod0 tmr tmrlr tot en tin 2 3 3 clk clk internal data bus 16-bit reload register reload control circu it reload signal 16-bit timer register uf wait signal count clock generation circuit machine clock prescaler gate input valid clock decision circuit output to internal peripheral functions output control circuit internal clock clear pin pin input control circuit clock selector output signal generation circuit external clock select function select signal operation control circuit generation circuit timer control status register (tmcsr) interrupt request output
mb90455 series 38 ds07-13728-5e 6. watch timer outline the watch timer is a 15-bit free-run counter th at increments in synchronization with sub clock. ? interval time is selectable among 7 choices, and gener ation of interrupt request is allowed for each interval. ? provides operation clock to the subclock os cillation stabilizing wait timer and watchdog timer. ? always uses subclock as a count clock regardless of settings of clock selection register (ckscr). ? interval timer function ? in the watch timer, a bit corresponding to the interval ti me overflows (carry-over) when an interval time, which is specified by interval time selection bit, is reac hed. then overflow flag bit is set (wtc: wtof=1). ? if an interrupt by overflow is permitted (wtc: wtie=1), an interrupt request is generated upon setting an overflow flag bit. ? interval time of watch timer is select able among the following seven choices : ? interval time of watch timer sclk: sub clock frequency values in parentheses ?( )? are calculat ion when operating with 8.192 khz clock. sub clock cycle interval time 1/sclk (122 s) 2 8 /sclk (31.25 ms) 2 9 /sclk (62.5 ms) 2 10 /sclk (125 ms) 2 11 /sclk (250 ms) 2 12 /sclk (500 ms) 2 13 /sclk (1.0 s) 2 14 /sclk (2.0 s)
mb90455 series ds07-13728-5e 39 ? watch timer block diagram actual interrupt request number of watch timer is as follows : interrupt request number : #28 (1c h ) ? watch timer counter a 15-bit up counter that uses sub clock (sclk) as a count clock. ? counter clear circuit a circuit that clears the watch timer counter. wtof wtr wtc1 wtc0 wtc2 wdcs sce wtie 2 5 2 4 2 3 2 1 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 8 2 7 2 6 2 2 sclk of of ofof of of of of to watchdog timer watch timer counter power-on reset shift to hardware standby shift to stop mode to sub clock oscillation stabilizing wait time interval timer selector watch timer interrupt of : overflow sclk : sub clock watch timer control register (wtc) counter clear circuit
mb90455 series 40 ds07-13728-5e 7. 8/16-bit ppg timer outline the 8/16-bit ppg timer is a 2-channe l reload timer module (ppg0 and ppg1) that allows outputting pulses of arbitrary cycle and duty cycle. comb ination of the two channels allows selection among the following operations: ? 8-bit ppg output 2-channel independent operation mode ? 16-bit ppg output operation mode ? 8-bit and 8-bit ppg output operation mode mb90455 series device has two 8/16-bit built-in ppg ti mers. this section describes functions of ppg0/1. ppg2/3 have the same functions as those of ppg0/1. ? functions of 8/-16-bit ppg timer the 8/-16-bit ppg timer is composed of four 8-bit relo ad register (prlh0/prll0, prlh1/prll1) and two ppg down counters (pcnt0, pcnt1). ? widths of ?h? and ?l? in output pulse are specifiabl e independently. cycle and duty factor of output pulse is specifiable arbitrarily. ? count clock is selectable among 6 internal clocks. ? the timer is usable as an interval timer, by generating interrupt req uests for each interval. ? the time is usable as a d/a converter, with an external circuit.
mb90455 series ds07-13728-5e 41 ? 8/16-bit ppg timer0 block diagram ppg0 clk r sq pen0 pe0 pie0 puf0 pcs2 pcs0 pcm2 pcm1 pcm0 pcs1 3 2 re- served re- versed ?h? level side data bus ?l? level side data bus ppg0 reload register ppg0 operation mode control register (ppgc0) interrupt request output* operation mode control signal select signal reload register l/h selector pplh0 (?h? level side) ppll0 (?l? level side) ppg0 temporary buffer 0(prlbh0) count start value reload clear ppg0 down counter (pcnt0) underflow ppg1 underflow ppg0 underflow (to ppg1) pulse selector ppg0 output latch ppg output control circuit pin time-base timer output (512/hclk) peripheral clock (1/ ) peripheral clock (2/ ) peripheral clock (4/ ) peripheral clock (8/ ) peripheral clock (16/ ) count clock selector select signal ppg0/1 count clock selection register (ppg01) ? : undefined reserved : reserved bit hclk : oscillation clock frequency : machine clock frequency * : interrupt output of 8/16-bit ppg timer 0 is incorporated into one by the or circuit against interrupt output of 8/16-bit ppg timer 1.
mb90455 series 42 ds07-13728-5e ? 8/16-bit ppg timer 1 block diagram clk md0 r sq pen1 pe1 pie1 puf1 md1 md0 pcs2 pcs0 pcm2 pcm1 pcm0 pcs1 3 2 ppg1 re- versed re- served ?h? level side data bus ?l? level side data bus ppg1 reload register ppg1 operation mode control register (ppgc1) interrupt request output* select signal reload selector l/h selector prlh1 (?h? level side) prll1 (?l? level side) ppg1 temporary buffer 0(prlbh1) count start value reload clear ppg1 down counter (pcnt1) under- flow ppg1 output latch ppg output control circuit pin time-base timer output (512/hclk) peripheral clock (1/ ) peripheral clock (2/ ) peripheral clock (4/ ) peripheral clock (8/ ) peripheral clock (16/ ) count clock selector select signal ppg0/1 count clock selection register (ppg01) ? : undefined reserved : reserved bit hclk : oscillation clock frequency : machine clock frequency * : interrupt output of 8/16-bit ppg timer 1 is incorporated into one by the or circuit against interrupt output of 8/16-bit ppg timer 0. operation mode control signal ppg1 underflow (to ppg0) ppg0 underflow (from ppg0)
mb90455 series ds07-13728-5e 43 8. delay interrupt generation module outline the delay interrupt generation module is a module that generates interrupts for switching tasks. generation of a hardware interrupt request is performed by software. ? delay interrupt generation module outline using the delay interrupt generation module, hardware in terrupt request is generated and released by software. delay interrupt generation module outline ? delay interrupt generation module block diagram ? interrupt request latch a latch that retains settings on delay interrupt request ge neration/release register (generation or release of delay interrupt request). ? delay interrupt request gene ration/release register (dirr) generates or releases delay interrupt request. ? interrupt number. an interrupt number used in delay inte rrupt generation module is as follows: interrupt number: #42 (2a h ) function and control cause of interrupt set ?1? in r0 bit of delay interrupt reques t generation/release register (dirr: r0=1), generating an interrupt request. set ?0? in r0 bit of delay interrupt reques t generation/release register (dirr: r0=0), releasing an interrupt request. interrupt number #42 (2a h ) interrupt control no setting of permission register is provided. interrupt flag retained in dirr: r0 bit ei 2 os not ready for expanded intelligent i/o service. r0 internal data bus delay interrupt request generation/release register (dirr) ? : not defined s interrupt request r latch interrupt request signal
mb90455 series 44 ds07-13728-5e 9. dtp/external interrupt outline dtp/external interrupt transfers an interrupt request generat ed by an external peripheral device or a data trans- mission request to cpu, generating external interrupt request and activating expan ded intelligent i/o service. ? dtp/external interrupt function an interrupt request input from external peripheral device to external input pins (int7 to int4), just as interrupt request of peripheral device, generates an interrupt requ est. the interrupt request generates an external interrupt and activates expanded intelligent i/o service (ei 2 os). if the expanded intelligent i/o service (ei 2 os) has been disabled by interrupt control register (icr: ise=0), external interrupt function is enabl ed and branches to interrupt processing. if the ei 2 os has been enabled, (icr: ise=1) , dtp function is enabled and au tomatic data transmission is performed by ei 2 os. after performing specified number of data transmission processes, the process branches to interrupt processing. dtp/external interrupt external interrupt dtp function input pin 4 pins (int4 to int7) interrupt cause specify for each pin with detection level setting register (elvr). input of ?h? level/?l? level/rising edge/falling edge. input of ?h? level/ ?l? level interrupt number #24 (18 h ) , #27 (1b h ) interrupt control enabling or disabling output of interrupt re quest, using dtp/external interrupt permission register (enir). interrupt flag retaining interrupt cause with dt p/external interrupt cause register (eirr). process selection disable ei 2 os (icr: ise=0) enable ei 2 os (icr: ise=1) process branch to external interrupt process after automatic data transmission by ei 2 os for specified number of times, branch to interrupt process.
mb90455 series ds07-13728-5e 45 ? dtp/external interrupt block diagram la4lb4la5lb5la6lb6la7lb7 en4en5en6en7 er4er5er6er7 int7 int6 int5 int4 re- served re- served re- served re- served detection level setting register (elvr) level/edge selector pin pin pin pin dtp/external interrupt input detection circuit interrupt request signal dtp/external interrupt cause register (eirr) dtp/external interrupt permission register (enir) level/edge selector level/edge selector level/edge selector internal data bus
mb90455 series 46 ds07-13728-5e 10. 8/10-bit a/d converter the 8/10-bit a/d converter converts an analog input volta ge into 8-bit or 10/bit digital value, using the rc-type successive approximation conversion method. ? input signal is selected among 8 channels of analog input pins. ? activation trigger is selected among software tr igger, internal timer output, and external trigger. ? functions of 8/10-bit a/d converter the 8/10-bit a/d converter converts an analog voltage (input voltage) input to analog input pin into an 8-bit or 10-bit digital value (a/d conversion). the 8/10-bit a/d converter has the following functions: ? a/d conversion takes a minimum of 6.12 s*1 for one channel, including sa mpling time. (a/d conversion) ? sampling of one channel takes a minimum of 2.0 s*. ? rc-type successive approximation conversion method, wi th sample & hold circuit is used for conversion. ? resolution of either 8 bits or 10 bits is specifiable. ? a maximum of 8 channels of analog input pins are allowed for use. ? generation of interrupt request is allowed, by st oring a/d conversion result in a/d data register. ? activation of ei 2 os is allowed upon occurrence of an interrupt request. with use of ei 2 os, data loss is avoided even if a/d conversion is performed successively. ? an activation trigger is selectable among software trigger, internal timer output, and external trigger (fall edge). *: when operating with 16-mhz machine clock ? 8/10-bit a/d converter conversion mode conversion mode description singular conversion mode the a/d conversion is performed form a star t channel to an end channel sequentially. upon completion of a/d conversion on an end channel, a/d conversion function stops. sequential conversion mode the a/d conversion is performed form a star t channel to an end channel sequentially. upon completion of a/d conversion on an end channel, a/d conversion function resumes from the start channel. pausing conversion mode the a/d conversion is performed by pausing at each channel. upon completion of a/d conversion on an end channel, a/d conversi on and pause functions resume from the start channel.
mb90455 series ds07-13728-5e 47 ? 8/10-bit a/d converter block diagram inte int paus sts1 sts0 strt busy ans2 md0 ans1 ans0 ane2 ane1 ane0 md1 avr avcc avss an0 an1 an2 an3 an4 an5 an6 an7 to adtg st0st1 ct1 ct0 d9 d8 s10 d5d6 d4 d3 d2 d1 d0 d7 2 6 2 2 2 re- served interrupt request output a/d control status register (adcs) activation selector decoder control circuit sample& hold circuit comparator analog channel selector d/a converter a/d data register (adcr) to : internal timer output ? : not defined reserved : be sure to set to ?0? : machine clock internal data bus
mb90455 series 48 ds07-13728-5e 11. uart outline uart is a general-purpose serial data communication interface for synchronous and asynchronous communi- cation using external devices. ? provided with bi-directional communication function for both clock-synchronous and clock-asynchronous modes. ? provided with master/slave communication function (mul ti-processor mode). (only master side is available.) ? interrupt request is generated upon completion of re ception, completion of tr ansmission and detection of reception error. ? ready for expanded intelligent service, ei 2 os. uart functions note : start/stop bit is not added upon clock-synchr onous transmission. data only is transmitted. uart operation modes ? : disallowed *1 : ?+1? is an address/data se lection bit used for communication cont rol (bit 11 of scr1 register: a/d) *2 : only 1 bit is detected as a stop bit on data reception. description data buffer full-duplex double buffer transmission mode clock synchronous (no start/stop bit, no parity bit) clock asynchronous (start-stop synchronous) baud rate built-in special-purpose baud-rate generator. setting is selectable among 8 values. input of external values is allowed. use of clock from external timer (16-bit reload timer 0) is allowed. data length 7 bits (only asynchronous normal mode) 8 bits signaling system non return to zero (nrz) system reception error detection framing error overrun error parity error (not detectable in operation mode 1 (multi-processor mode)) interrupt request receive interrupt (reception completed, reception error detected) transmission interrupt (transmission completed) ready for expanded intelli gent i/o service (ei 2 os) in both transmis- sion and reception master/slave communication function (asynchronous, multi-processor mode) communication between 1 (master) and n (slaves) are available (usable as master only). operation mode data length synchronization stop bit length with parity without parity 0 asynchronous mode (normal mode) 7-bit or 8-bit asynchronous 1- bit or 2-bit * 2 1 multi processor mode 8+1 *1 ? asynchronous 2 synchronous mode 8 ? synchronous no
mb90455 series ds07-13728-5e 49 ? uart block diagram sin1 sck1 sot1 md1 md0 cs2 cs1 scke soe tdre bds pen p sbl cl a/d rec rxe cs0 txe rie tie pe ore fre rdrf rst md div2 div1 div0 control bus special-purpose baud-rate generator 16-bit reload timer clock selector pin reception clock reception control circuit transmission control circuit start bit detection circuit transmission start circuit transmission bit counter transmission parity counter transmission clock reception interrupt request output transmission interrupt request output reception bit counter reception parity counter pin pin shift register for reception serial input data register 1 shift register for transmission serial output data register 1 start transmission recep- tion com- pleted reception error occurrence signal for ei 2 os (to cpu) reception status decision circuit internal data bus communi- cation prescaler control register serial mode register 1 serial control register 1 serial status register 1
mb90455 series 50 ds07-13728-5e 12. address matching detection function outline the address matching detection function checks if an address of an instruction to be processed next to a currently- processed instruction is identical with an address specif ied in the detection addres s register. if the addresses match with each other, an instruction to be processed next in program is forcibly replaced with int9 instruction, and process branches to the interrupt process program. using int9 interrupt, this function is available for correcting program by batch processing. ? address matching detection function outline ? an address of an instruction to be processed next to a currently-processed instruction of the program is always retained in an address latc h via internal data bus. by the address matching detection function, the address value retained in the address latch is always compared with an address specified in detection address setting register. if the compared address values match with ea ch other, an instruction to be processed next by cpu is forcibly replaced with int9 instruction, and an interrupt process program is executed. ? two detection address setting registers are provided (padr0 and padr1), and each register is provided with interrupt permission bit. generation of interrupt, which is caused by address matching between the address retained in address latch and the addr ess specified in address setting register, is permitted and prohibited on a register-by-register basis. ? address matching detection function block diagram ? address latch retains address value output to internal data bus. ? address detection control register (pacsr) specifies if interrupt is permitted or pr ohibited when addresses match with each other. ? detection address setting (padr0, padr1) specifies addresses to be compar ed with values in address latch. padr0 24bit ad1e ad0e pacsr padr1 24bit reserved reserved reserved reserved reserved reserved address latch detection address setting register 0 detection address setting register 1 int9 instruction (generate int9 interrupt) address detection control register (pacsr) reserved: be sure to set to ?0.? internal data bus comparator
mb90455 series ds07-13728-5e 51 13. rom mirror function selection module outline the rom mirror function selection module sets the data in rom assigned to ff bank so that the data is read by access to 00 bank. ? rom mirror function selection module block diagram ? ff bank access by rom mirror function rom mi reserved reserved reserved reserved reserved reserved reserved rom mirror function selection register (romm) address data address area ff bank 00 bank internal data bus ffffff h ff4000 h ff0000 h feffff h 00ffff h 004000 h fc0000 h fbffff rom mirror area 00 bank ff bank (rom mirror applicable area)
mb90455 series 52 ds07-13728-5e 14. 192 k/256 k/512 kbit flash memory outline the following three methods are provided for data writing and deleting on flash memory: 1. parallel writer 2. serial special-purpose writer 3. writing/deleting by program execution ? 192 k/256 k/512 kbit flash memory outline the 192 k/256 k/512k-bit flas h memory is allocated on ff h bank of cpu memory map. using the function of flash memory interface circuit, the memory allo ws read access and program access from cpu. writing/deleting on flash memory is performed by inst ruction from cpu via flash memory interface. because rewriting is allowed on mounted memory, modifying program and data is performed efficiently. ? features of 192 k/256 k/ 512 kbit flash memory ? dividing into many sectors ? automatic program algorithm (embedded algorithm: similar to mbm29lv200.) ? built-in deletion pause/deletion resume function ? detection of completed writing/delet ing by data polling and toggle bits. ? detection of completed writ ing/deleting by cpu interrupt. ? deletion is allowed on a sector-by-sect or basis (sectors are combined freely). ? number of writing/deleting operations (minimum): 10,000 times ? sector protection ? extended sector protection ? temporary sector unprotection note : a function of reading manufacture code and device code is not provided. thes e codes are not accessible by command either. ? flash memory writing/deleting ? writing and reading data is not allowed simultaneously on the flash memory. ? data writing and deleting on the flash memory is per formed by the processes as follows: make a copy of program on flash memory onto ram. then, execute the program copied on the ram. ? list of registers and reset values in flash memory 00 00 0x 00 76 bit 543210 : undefined flash memory control status register (fmcs)
mb90455 series ds07-13728-5e 53 ? sector configuration of 19 2 k/256 k/512 kbit flash memory ffa000 h ffbfff h ffc000 h ffffff h 7a000 h 7bfff h 7c000 h 7ffff h ff8000 h ff9fff h ffa000 h ffbfff h ffc000 h ffffff h 78000 h 79fff h 7a000 h 7bfff h 7c000 h 7ffff h ff0000 h ff7fff h ff8000 h ff9fff h ffa000 h ffbfff h ffc000 h ffffff h 70000 h 77fff h 78000 h 79fff h 7a000 h 7bfff h 7c000 h 7ffff h flash memory cpu address writer address* sa2 (16 kbytes) sa3 (16 kbytes) sa0 (8 kbytes) sa1 (16 kbytes) * : ?writer address? is an address equiv alent to cpu address, which is used when data is written on flash memory, using parallel writer. when writing/ deleting data with general-purpose writer, the writer address is used for writing and deleting. flash memory cpu address writer address* flash memory cpu address writer address* sa0 (8 kbytes) sa1 (8 kbytes) sa2 (8 kbytes) sa0 (32 kbytes) sa1 (8 kbytes) ? sector configuration of 192 kbit to flash memory (mb90f455 (s) ) ? sector configuration of 256 kbit to flash memory (mb90f456 (s) ) ? sector configuration of 512 kbit to flash memory (mb90f457 (s) )
mb90455 series 54 ds07-13728-5e electric characteristics 1. absolute maximum rating (v ss = av ss = 0.0 v) *1 : avcc and avr should not exceed vcc. also avr should not exceed avcc. *2 : v i , v o , should not exceed vcc + 0.3v. *3 : a peak value of an applicable one pi n is specified as a maximum output current. *4 : an average current value of an applicable one pin with in 100 ms is specified as an average output current. (average value is found by multiplying operating current by operating rate.) *5 : an average current value of all pins within 100 ms is specified as an average total output current. (average value is found by multiplying op erating current by operating rate.) (continued) parameter symbol rating unit remarks min max power supply voltage v cc v ss ? 0.3 v ss + 6.0 v av cc v ss ? 0.3 v ss + 6.0 v v cc = av cc * 1 avr v ss ? 0.3 v ss + 6.0 v av cc avr* 1 input voltage v i v ss ? 0.3 v ss + 6.0 v *2 output voltage v o v ss ? 0.3 v ss + 6.0 v *2 maximum clamp current i clamp ? 2.0 + 2.0 ma *6 total maximum clamp current | i clamp | ? 20 ma *6 ?l? level maximum output current i ol1 ? 15 ma normal output* 3 i ol2 ? 40 ma high-current output* 3 ?l? level average output current i olav1 ? 4 ma normal output* 4 i olav2 ? 30 ma high-current output* 4 ?l? level maximum total output current i ol1 ? 125 ma normal output i ol2 ? 160 ma high-current output ?l? level average total output current i olav1 ? 40 ma normal output* 5 i olav2 ? 40 ma high-current output* 5 ?h? level maximum output current i oh1 ?? 15 ma normal output* 3 i oh2 ?? 40 ma high-current output* 3 ?h? level average output current i ohav1 ?? 4 ma normal output* 4 i ohav2 ?? 30 ma high-current output* 4 ?h? level maximum total output current i oh1 ?? 125 ma normal output i oh2 ?? 160 ma high-current output ?h? level average total output current i ohav1 ?? 40 ma normal output* 5 i ohav2 ?? 40 ma high-current output* 5 power consumption p d ? 245 mw operating temperature t a ?40 + 105 c storage temperature tstg ?55 + 150 c
mb90455 series ds07-13728-5e 55 (continued) *6 : ? applicable to pins: p10 to p17, p20 to p27, p30 to p33, p35*, p 36*, p37, p40 to p44, p50 to p57 note : p35 and p36 are applicable only for pr oducts of mb90f455s/f456s/f457s, mb90455s/456s/457s. ? use within recommended operating conditions. ? use at dc voltage (current) . ? the +b signal should always be applied a lim iting resistance placed between the + b signal and the microcontroller. ? the value of the limiting resistance should be set so that when the +b signal is applied the input current to the microcontroller pin does not exceed rated values , either instantaneously or for prolonged periods. ? note that when the microcontroller drive current is low, such as in the power saving modes, the + b input potential may pass through the protective di ode and increase the potential at the v cc pin, and this may affect other devices. ? note that if a +b signal is input when the microcontroller power supply is off (not fixed at 0 v) , the power supply is provided from the pins, so that incomplete operation may result. ? note that if the + b input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be suff icient to operate the power-on reset. ? care must be taken not to leave the +b input pin open. ? note that analog system input/output pins other than the a/d input pins (lcd drive pins, comparator input pins, etc.) cannot accept + b signal input. ? sample recommended circuits: warning: semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute ma ximum ratings. do not exceed these ratings. p-ch n-ch v cc r ? input/output equivalent circuits +b input (0 v to 16 v) limiting resistance protective diode
mb90455 series 56 ds07-13728-5e 2. recommended operating conditions (v ss = av ss = 0.0v) *1 : use a ceramic capacitor, or a capacitor of similar frequency characteristics. on the vcc pin, use a bypass capacitor that has a larger capacity than that of cs. refer to the following figure for conn ection of smoothing capacitor cs. *2 : avcc is a voltage at which accuracy is guaranteed. avcc should not exceed vcc. warning: the recommended operating co nditions are required in order to ensure the normal operation of the semiconductor device. all of the device's el ectrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outs ide the listed conditions are advised to contact their representatives beforehand. parameter symbol value unit remarks min typ max power supply voltage v cc 3.5 5.0 5.5 v under normal operation 3.0 ? 5.5 v retain status of stop operation av cc 4.0 ? 5.5 v *2 smoothing capacitor c s 0.1 ? 1.0 f*1 operating temperature t a ?40 ?+ 105 c c c s ? c pin connection diagram
mb90455 series ds07-13728-5e 57 3. dc characteristics (v cc = 5.0 v 10%, v ss = av ss = 0.0 v, t a = ?40 c to + 105 c) (continued) parame- ter sym- bol pin name conditions value unit remarks min typ max ?h? level input voltage v ihs cmos hysteresis input pin ? 0.8 v cc ?v cc + 0.3 v v ihm md input pin ? v cc ? 0.3 ? v cc + 0.3 v ?l? level input voltage v ils cmos hysteresis input pin ?v ss ? 0.3 ? 0.2 v cc v v ilm md input pin ? v ss ? 0.3 ? v ss + 0.3 v ?h? level output voltage v oh1 pins other than p14 to p17 v cc = 4.5 v, i oh = ?4.0 ma v cc ? 0.5 ? ? v v oh2 p14 to p17 v cc = 4.5 v, i oh = ?14.0 ma v cc ? 0.5 ? ? v ?l? level output voltage v ol1 pins other than p14 to p17 v cc = 4.5 v, i ol = 4.0 ma ??0.4v v ol2 p14 to p17 v cc = 4.5 v, i ol = 20.0 ma ??0.4v input leak current i il all input pins v cc = 5.5 v, v ss < v i < v cc ?5 ? + 5 a power supply current* i cc v cc v cc = 5.0 v, internally operating at 16 mhz, normal operation. ?2530ma v cc = 5.0 v, internally operating at 16 mhz, writing on flash memory. ?4550ma flash rom product v cc = 5.0 v, internally operating at 16 mhz, deleting on flash memory. ?4550ma flash rom product i ccs v cc = 5.0 v, internally operating at 16 mhz, sleeping. ?812ma i cts v cc = 5.0 v, internally operating at 2 mhz, transition from main clock mode, in time-base timer mode. ? 0.75 1.0 ma flash rom product 0.2 0.35 ma mask rom product
mb90455 series 58 ds07-13728-5e (continued) (v cc = 5.0 v 10%, v ss = av ss = 0.0 v, t a = ?40 c to + 105 c) * : test conditions of power supply current ar e based on a device using external clock. parame- ter sym- bol pin name conditions rating unit remarks min typ max power supply current* i ccl v cc v cc = 5.0 v, internally operating at 8 khz, subclock operation, t a = + 25 c ?0.31.2ma flash rom product ? 40 100 a mask rom product i ccls v cc = 5.0 v, internally operating at 8 khz, subclock, sleep mode, t a = + 25 c ?1030 a i cct v cc = 5.0 v, internally operating at 8 khz, watch mode, t a = + 25 c ?825 a i cch stopping, t a = + 25 c ?520 a input capacity c in other than av cc , av ss , avr, c, v cc , v ss ? ? 5 15 pf pull-up resistor r up rst ? 25 50 100 k pull-down resistor r down md2 ? 25 50 100 k flash rom product is not provided with pull-down resistor.
mb90455 series ds07-13728-5e 59 4. ac characteristics (1) clock timing (v cc = 5.0 v 10%, v ss = av ss = 0.0 v, t a = ?40 c to + 105 c) *1 : internal operation clock frequency should not exceed 16 mhz. *2 : when selecting the pll clock, the range of clock freque ncy is limited. use this product within range as mentioned in ?relation among external clock frequency and internal clock frequency?. parameter symbol pin name value unit remarks min typ max clock frequency f c x0, x1 3?8mhz when crystal or ceramic resonator is used* 2 3 ? 16 mhz external clock * 1, * 2 4 ? 16 mhz pll multiplied by 1* 2 4 ? 8 mhz pll multiplied by 2* 2 4 ? 5.33 mhz pll multiplied by 3* 2 4 ? 4 mhz pll multiplied by 4* 2 f cl x0a, x1a ? 32.768 ? khz clock cycle time t hcyl x0, x1 125 ? 333 ns t lcyl x0a, x1a ? 30.5 ? s input clock pulse width p wh , p wl x0 10 ? ? ns set duty factor at 30% to 70% as a guideline. p wlh ,p wll x0a ? 15.2 ? s input clock rise time and fall time t cr , t cf x0 ? ? 5 ns when external clock is used internal operation clock frequency f cp ? 1.5 ? 16 mhz when main clock is used f lcp ? ? 8.192 ? khz when sub clock is used internal operation clock cycle time t cp ? 62.5 ? 666 ns when main clock is used t lcp ? ? 122.1 ? s when sub clock is used x0 t hcyl t cf t cr 0.8 v cc 0.2 v cc p wh p wl x0a t lcyl t cf t cr 0.8 v cc 0.2 v cc p wlh p wll ? clock timing
mb90455 series 60 ds07-13728-5e rating values of alternating current is defined by the measurement reference voltage values shown below: 16 12 8 9 4 34 8 16 5.5 4.0 3.0 3.5 34 8 16 12 1.5 power voltage v cc (v) internal clock f cp (mhz) operation guarantee range of mb 90f455 (s) /f456 (s) /f457 (s) and mb90455 (s) /456 (s) /457 (s) pll operation guarantee range internal clock f cp (mhz) external clock f c (mhz)* multiply by 4 multiply by 3 multiply by 2 multiply by 1 x1/2 (no multiplication) relation between internal operation clock frequency and power supply voltage relation among external clock frequency and internal clock frequency ? pll operation guarantee range a/d converter accuracy guarantee range * : fc is 8 mhz at maximum when crystal or ceramic resonator is used. 0.8 v cc 0.2 v cc 2.4 v 0.8 v hysteresis input pin ? output signal waveform output pin ? input signal waveform
mb90455 series ds07-13728-5e 61 (2) reset input timing *1 : oscillation time of oscillator is time until oscillation reaches 90% of amplit ude. it takes several milliseconds to several dozens of milliseconds on a crystal oscillator, several hundreds of microsec onds to several milliseconds on a ceramic oscillator, and 0 milliseconds on an external clock. *2 : except for mb90f455s/f456s /f457s, mb90455s/456s/457s. *3 : refer to "(1) clock timing" ratings for t cp (internal operation clock cycle time). parameter sym- bol pin name condi- tions value unit remarks min max reset input time t rstl rst ? 16 t cp * 3 ? ns normal operation oscillation time of oscillator* 1 + 100 s + 16 t cp * 3 ?? in sub clock* 2 , sub sleep* 2 , watch* 2 and stop mode 100 ? s in time base timer mode t rstl 0.2 v cc 0.2 v cc 100 s + 16 t cp rst x0 ? in sub clock, sub sleep, watch and stop mode internal operation clock internal reset oscillation time of oscillator wait time for stabilizing oscillation execute instruction 90% of amplitude
mb90455 series 62 ds07-13728-5e (3) power-on reset (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ?40 c to + 105 c) parameter symbol pin name conditions value unit remarks min max power supply rise time t r v cc ? 0.05 30 ms power supply shutdown time t off v cc 1 ? ms waiting time until power-on v cc v cc v ss 3.0 v t r t off 2.7 v 0.2 v 0.2 v 0.2 v sudden change of power supply voltage may ac tivate the power-on reset function. when changing power supply voltages during operat ion, raise the power smoothly by suppressing variation of voltages as show n below. when raising the power, do not use pll clock. howev- er, if voltage drop is 1v/s or less, us e of pll clock is allowed during operation. limiting the slope of rising within 50 mv/ms is recommended. ram data hold period
mb90455 series ds07-13728-5e 63 (4) uart timing (v cc = 4.5 v to 5.5 v, v ss = 0.0 v, t a = ?40 c to + 105 c) * : refer to "(1) clock timing" ratings for t cp (internal operation clock cycle time). notes: ? ac rating in clk synchronous mode. ? c l is a load capacitance value on pins for testing. parameter symbol pin name conditions value unit remarks min max serial clock cycle time t scyc sck1 internal shift clock mode output pin is : cl = 80 pf+1ttl. 8 t cp * ? ns sck sot delay time t slov sck1, sot1 ?80 + 80 ns valid sin sck t ivsh sck1, sin1 100 ? ns sck valid sin hold time t shix sck1, sin1 60 ? ns serial clock ?h? pulse width t shsl sck1 external shift clock mode output pin is : cl = 80 pf+1ttl. 4 t cp * ? ns serial clock ?l? pulse width t slsh sck1 4 t cp * ? ns sck sot delay time t slov sck1, sot1 ? 150 ns valid sin sck t ivsh sck1, sin1 60 ? ns sck valid sin hold time t shix sck1, sin1 60 ? ns
mb90455 series 64 ds07-13728-5e ? internal shift clock mode sck1 s ot1 sin1 t scyc t s lov t ivsh t shix 0.8 v0 . 8 v 2.4 v 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc ? external shift clock mode sck1 s ot1 sin1 t slsh t shsl t s lov t ivsh t shix 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc
mb90455 series ds07-13728-5e 65 (5) timer input timing (v cc = 4.5 v to 5.5 v, v ss = 0.0 v, t a = ?40 c to + 105 c) * : refer to "(1) clock timing" ratings for t cp (internal operation clock cycle time). (6) trigger input timing (v cc = 4.5 v to 5.5 v, v ss = 0.0 v, t a = ?40 c to + 105 c) * : refer to "(1) clock timing" ratings for t cp (internal operation clock cycle time). parameter symbol pin name conditions value unit remarks min max input pulse width t tiwh tin0, tin1 ? 4 t cp * ? ns t tiwl in0 to in3 parameter symbol pin name conditions value unit remarks min max input pulse width t trgh t trgl int4 to int7, adtg ? 5 t cp * ? ns 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t tiwh t tiwl tin0, tin1, in0 ~ in3 ? timer input timing 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t trgh t trgl int4 ~ int7, adtg ? trigger input timing
mb90455 series 66 ds07-13728-5e 5. a/d converter (v cc = av cc = 5.0 v 10 % , v ss = av ss = 0.0 v, 3.0 v avr ? av ss , t a = ?40 c to + 105 c) *1 : refer to "(1) clock timing" ratings for t cp (internal operation clock cycle time). *2 : if a/d converter is not operating, a current wh en cpu is stopped is applicable (vcc=avcc=avr=5.0 v). parameter symbol pin name conditions value unit remarks min max resolution ?? ? ? 10 bit total error ?? ? ? 3.0 lsb nonlinear error ?? ? ? 2.5 lsb differential linear error ?? ? ? 1.9 lsb zero transition voltage v ot an0 to an7 av ss ? 1.5 lsb av ss + 0.5 lsb av ss + 2.5 lsb v 1 lsb = (avr ? av ss ) / 1024 full-scale transition voltage v fst an0 to an7 avr ? 3.5 lsb avr ? 1.5 lsb avr + 0.5 lsb v compare time ?? 66 t cp * 1 ?? ns with 16 mhz machine clock 5.5 v av cc 4.5 v 88 t cp * 1 ?? ns with 16 mhz machine clock 4.5 v > av cc 4.0 v sampling time ?? 32 t cp * 1 ?? ns with 16 mhz machine clock 5.5 v av cc 4.5 v 128 t cp * 1 ?? ns with 16 mhz machine clock 4.5 v > av cc 4.0 v analog port input current i ain an0 to an7 ?? 10 a analog input voltage v ain an0 to an7 av ss ? avr v reference voltage ? avr av ss + 2.7 ? av cc v power supply current i a av cc ? 3.5 7.5 ma i ah av cc ?? 5 a*2 reference voltage supplying current i r avr ? 165 250 a i rh avr ?? 5 a*2 variation among channels ? an0 to an7 ?? 4lsb
mb90455 series ds07-13728-5e 67 6. definition of a/d converter terms (continued) resolution : analog variation that is recognized by an a/d converter. linear error : deviation between a line acro ss zero-transition line (?00 0000 00 0 0? ?00 0000 0001?) and full-scale transition line (?11 1111 11 1 0? ?11 1111 1111?) and actual conversion characteristics. differential linear error : deviation of input voltage, that is required for changing output code by 1 lsb, from an ideal value. total error : difference between an actual value and an ideal value. a total error includes zero transition error, full-scale transition error, and linear error. 3ff 3fe 3fd 004 003 002 001 avss avr 1.5 lsb 0.5 lsb {1 lsb (n ? 1) + 0.5 lsb} v nt total error total error of digital output ?n? = v nt ? {1 lsb (n ? 1) + 0.5 lsb} [lsb] 1 lsb 1 lsb = (ideal value) avr ? av ss [v] 1024 v ot (ideal value) = av ss + 0.5 lsb [v] v fst (ideal value) = avr ? 1.5 lsb [v] v nt : a voltage at which digital output transits from (n-1) to n. digital output actual conversion characteristics (actually-measured value) actual conversion characteristics analog input ideal characteristics
mb90455 series 68 ds07-13728-5e (continued) 3ff 3fe 3fd 004 003 002 001 avss avr avss avr n + 1 n n ? 1 n ? 2 v ot (actual measurement value) v fst (actual measurement value) actual conversion characteristics {1 lsb (n ? 1) + v ot } actual conversion characteristics ideal characteristics ideal characteristics actual conversion characteristics v ( n + 1) t (actual measurement value) v nt (actual measurement value) actual conversion characteristics v nt (actual measurement value) differential linear error linear error linear error of digital output n = v nt ? {1 lsb (n ? 1) + v ot } 1 lsb [lsb] differential linear error of digital output n = v ( n + 1 ) t ? v nt 1 lsb ? 1lsb [lsb] v fst ? v ot 1022 [v] 1 lsb = v ot : voltage at which digital output transits from ?000 h ? to ?001 h .? v fst : voltage at which digital output transits from ?3fe h ? to ?3ff h .? digital output digital output analog input analog input
mb90455 series ds07-13728-5e 69 7. notes on a/d converter section use the device with external circuits of th e following output impedance for analog inputs: recommended output impedance of exter nal circuits are: approx. 3.9 k or lower (4.5 v avcc 5.5 v) (sampling period=2.00 s at 16-mhz machine clock), approx. 11 k or lower (4.0 v avcc < 4.5 v) (sampling period=8.0 s at 16-mhz machine clock). if an external capacitor is used, in consideration of the effect by tap capacitance caused by external capacitors and on-chip capacitors, capacitance of the external one is recommended to be several thousand times as high as internal capacitor. if output impedance of an external circuit is too high, a sampling period for an analog voltage may be insufficient. ? about errors as [avr-avss] become smaller, values of relative errors grow larger. 8. flash memory program/erase characteristics parameter conditions value unit remarks min typ max sector erase time t a = + 25 c v cc = 5.0 v ? 115s excludes 00 h programming prior to erasure chip erase time ? 4 ? s excludes 00 h programming prior to erasure word (16 bit width) programming time ? 16 3,600 s except for the over head time of the system program/erase cycle ? 10,000 ?? cycle c r ? analog input circuit model note : use the values in the figure only as a guideline. mb90f455 (s) /f456 (s) /f457 (s) and mb90455 (s) /456 (s) /457 (s) 4.5 v av cc 5.5 v r : = 2.35 k , c : = 36.4 pf 4.0 v av cc < 4.5 v r : = 16.4 k , c : = 36.4 pf comparator analog input
mb90455 series 70 ds07-13728-5e example characteristics ?mb90f457 (continued) i cc (ma) v cc (v) 2.5 3.5 4.5 5.5 6.5 0 5 10 15 20 25 30 f = 16 mhz f = 10 mhz f = 8 mhz f = 4 mhz f = 2 mhz i cc ? v cc t a = +25 c, external clock operation f = internal operation frequency i ccs (ma) v cc (v) 2.5 3.5 4.5 5.5 6.5 0 2 4 6 8 10 f = 16 mhz f = 10 mhz f = 8 mhz f = 4 mhz f = 2 mhz i ccs ? v cc t a = +25 c, external clock operation f = internal operation frequency i ccl (a) v cc (v) 3 4567 0 50 200 250 300 350 f = 8 khz 100 150 i ccl ? v cc t a = +25 c, external clock operation f = internal operation frequency
mb90455 series ds07-13728-5e 71 (continued) i ccls (a) v cc (v) 3 4567 0 3 9 11 13 15 f = 8 khz 5 7 1 4 6 8 10 12 14 2 i ccls ? v cc t a = + 25 c, external clock operation f = internal operation frequency i cct (a) v cc (v) 3 4567 0 6 9 10 f = 8 khz 2 4 1 3 5 7 8 i cct ? v cc t a = + 25 c, external clock operation f = internal operation frequency i cch ( a) v cc (v) 2 4567 0 30 5 10 15 20 25 3 i cch ? v cc stopping, t a = +25 c
mb90455 series 72 ds07-13728-5e (continued) l cc- v oh (mv) i oh (ma) 0 4681 0 0 600 900 1000 200 400 100 300 500 700 800 2 (v cc ? v oh ) ? i oh t a = +25 c, v cc = 4.5 v v ol (mv) i ol (ma) 0 4681 0 0 600 900 1000 200 400 100 300 500 700 800 2 v ol ? i ol t a = +25 c, v cc = 4.5 v v in (v) v cc (v) 2.5 3.5 4 4.5 6 0 3 5 1 2 4 3 5 5.5 v ih v il v in ? v cc t a = +25 c ?h? level input voltage/ ?l? level input voltage
mb90455 series ds07-13728-5e 73 ? mb90457 (continued) i cc ? v cc t a = +25 c, external clock operation f = internal operation frequency i cc (ma) v cc (v) 2.5 3.5 4 4.5 6 0 15 25 5 10 20 3 5 5.5 6.5 7 f = 10 mhz f = 16 mhz f = 8 mhz f = 4 mhz f = 2 mhz i ccs (ma) v cc (v) 2.5 3.5 4.5 0 5 9 2 3 7 5.5 6.5 f = 10 mhz f = 16 mhz f = 8 mhz f = 4 mhz f = 2 mhz 1 4 6 8 i ccs ? v cc t a = + 25 c, external clock operation f = internal operation frequency i ccl (a) v cc (v) 3 45 0 50 90 20 30 70 67 f = 8 khz 10 40 60 80 100 i ccl ? v cc t a = +25 c, external clock operation f = internal operation frequency
mb90455 series 74 ds07-13728-5e (continued) i ccls ( a) v cc (v) 3 45 0 5 9 2 3 7 67 f = 8 khz 1 4 6 8 10 i ccls ? v cc t a = +25 c, external clock operation f = internal operation frequency f = 8 khz i cct ( a) v cc (v) 3 56 0 5 9 2 3 7 7 1 4 6 8 10 4 i cct ? v cc t a = + 25 c, external clock operation f = internal operation frequency i cch ( a) v cc (v) 2 4567 0 30 5 10 15 20 25 3 i cch ? v cc stopping, t a = +25 c
mb90455 series ds07-13728-5e 75 (continued) v cc - v oh (mv) i oh (ma) 0 46 0 500 900 200 300 700 81 0 100 400 600 800 1000 2 13579 (v cc ? v oh ) ? i oh t a = +25 c, v cc = 4.5 v v ol (mv) i ol (ma) 0 46 0 500 900 200 300 700 81 0 100 400 600 800 1000 2 15 379 v ol ? i ol t a = + 25 c, v cc = 4.5 v v cc (v) 2.5 4 4.5 0 1 5.5 6 2 3 4 5 3 3.5 5 v in (v) v ih v il v in ? v cc t a = + 25 c ?h? level input voltage/ ?l? level input voltage
mb90455 series 76 ds07-13728-5e ordering information part number package remarks mb90f455pmt mb90f456pmt mb90f457pmt mb90455pmt mb90456pmt mb90457pmt mb90f455spmt mb90f456spmt mb90f457spmt mb90455spmt mb90456spmt MB90457SPMT 48-pin plastic lqfp (fpt-48p-m26)
mb90455 series ds07-13728-5e 77 package dimention please confirm the latest package dimension by following url. http://edevice.fujitsu.com/package/en-search/ 4 8 -pin plastic lqfp lea d pitch 0.50 mm p a ck a ge width p a ck a ge length 7 7 mm lea d s h a pe gu llwing s e a ling method plastic mold mou nting height 1.70 mm max weight 0.17 g code (reference) p-lfqfp48 -7 7-0.50 4 8 -pin plastic lqfp (fpt-4 8 p-m26) (fpt-48p-m26) c 2003 fujitsu limited f48040s-c-2-2 24 13 362 5 48 37 index sq 9.000.20(.354.008)sq 0.1450.055 (.006.002) 0.08(.003) "a" 0?~8? .059 ?.004 +.008 ?0.10 +0.20 1.50 0.600.15 (.024.006) 0.100.10 (.004.004) (stand off) 0.25(.010) details of "a" part 1 12 0.08(.003) m (.008.002) 0.200.05 0.50(.020) lead no. (mounting height) .276 ?.004 +.016 ?0.10 +0.40 7.00 * dimens ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s . ?2003 -2008 fujits u microelectronics limited f48 040s -c-2-3 note 1) * : these dimensions include resin protrusion. note 2) pin s width a nd pins thickness inclu de pla ting thickness. note 3 )pin s width do not inclu de tie bar cu tting rema inder.
mb90455 series 78 ds07-13728-5e main changes in this edition the vertical lines marked in the left side of the page show the changes. page section change results 5 product lineup corrected the channel construction for 8/ 16-bit ppg timer. ?one 16-bit channel? ?two 16-bit channels? 12 handling devices ? handling unused pins corrected the explanation. ?unused input pins? ?unused input/output pins? 59 electrical characteristics 4. ac characteristics (1) clock timing added the following item to value of clock frequency. pll multiplied by 1 to pll multiplied by 4 62 (3) power-on reset corrected the remark. repeated operation waiting time until power-on
mb90455 series ds07-13728-5e 79 memo
mb90455 series fujitsu microelectronics limited shinjuku dai-ichi seimei bldg ., 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0722, japan tel: +81-3-5322-3329 http://jp.fujitsu.com/fml/en/ for further information please contact: north and south america fujitsu microelectronics america, inc. 1250 e. arques avenue, m/s 333 sunnyvale, ca 94085-5401, u.s.a. tel: +1-408-737-5600 fax: +1-408-737-5999 http://www.fma.fujitsu.com/ europe fujitsu microelectronics europe gmbh pittlerstrasse 47, 63225 langen, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ korea fujitsu microelectronics korea ltd. 206 kosmo tower building, 1002 daechi-dong, gangnam-gu, seoul 135-280, republic of korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ asia pacific fujitsu microelectronics asia pte. ltd. 151 lorong chuan, #05-08 new tech park 556741 singapore tel : +65-6281-0770 fax : +65-6281-0220 http://www.fmal.fujitsu.com/ fujitsu microelectronics shanghai co., ltd. rm. 3102, bund center, no.222 yan an road (e), shanghai 200002, china tel : +86-21-6146-3688 fa x : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ fujitsu microelectronics pacific asia ltd. 10/f., world commerce centre, 11 canton road, tsimshatsui, kowloon, hong kong tel : +852-2377-0226 fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/ specifications are subject to change without notice. for further information please contact each office. all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with sales representatives before ordering. the information, such as descriptions of f unction and application circuit examples, in this document are presented solely for t he purpose of reference to show examples of operations and uses of fujitsu microelectronics device; fujitsu microelectronics does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incor porating the device based on such information, you must assume any re sponsibility arising out of such use of the information. fujitsu microelectronics assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of f unction and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu microelectroni cs or any third party or does fujitsu microelectronics warrant non-i nfringement of any third-party's intellectual property right o r other right by using such information. fujitsu microelectronics assumes no liability for any infringement of the intellectual property rights or other rights of third parties which w ould result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a ser ious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction con trol in nuclear facility, aircraft flight control, air tr affic control, mass transport control, me dical life support system, missile launch con trol in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu microelectronics will not be liable against you and/or any third party for any claims or damages arisi ng in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failure s by incorporating safety design measures into your facility and equi pment such as redundancy, fire protection, and prevention of ov er-current levels and other abnormal operating conditions. exportation/release of any products described in this document may require necessary procedures in accordance with the regulati ons of the foreign exchange and foreign trade control law of japan and/or us export control laws. the company names and brand names herein are the trademarks or registered trademarks of their respective owners. edited: sales promotion department

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